RTC part: Post-counter is 32 bit with 32768 Hz clock, and how to handle the overflow of Post-counter register

perryfather

@Who may concerned
I see the CXD5602 manual, the Post-counter is 32 bit with 32768 Hz clock. So it means every 36.4 Hours, the post-counter register will be over run.

May I know how Spresense handle the overflow of Post-counter register at Spresense SDK?
I dont know my assumption right or wrong ? Below is my assumption.
Will Spesense generate an interrupt when Post-counter register is overflow every 36.4 hours ? So Spresense will use this IRQ to correct the rtc saving time at ISR of this IRQ ?

TE-KarlKomierowski

@perryfather

Thanks for rising this question.

I started to look into this and can see that the interrupts are being handled by the low level drivers. But I stopped the investigation there for a while to continue on your number 2 question.,
According to page 170: CXD5602 user manual the RTC has two counters.

15 bit PreCounter that counts the 32,768Hz clocks, increments every 1/32768 seconds, overflows every second.
32 bit PostCounter is incremented every second. A 32 bit counter can have a maximum value of 4294967295. To translate this to a human understandable time gives me something in the range of 150 years before it will overflow. 0xFFFF / (3600 x 24 x 7 x 4 x 12) = 147,95 years
(32 bit max val / (sec/h x h/day x days/week x weeks/month x months/year))

I know that I didn't answer your question but I doubt that this will be an issue.

BR
Karl

@perryfather said in RTC part: Post-counter is 32 bit with 32768 Hz clock, and how to handle the overflow of Post-counter register:

.
Will Spesense generate an interrupt when Post-counter register is overflow every 36.4 hours ? So Spresense will use this IRQ to correct the rtc saving time at ISR of this IRQ ?