@Who may concerned
I see the CXD5602 manual, the Post-counter is 32 bit with 32768 Hz clock. So it means every 36.4 Hours, the post-counter register will be over run.
- May I know how Spresense handle the overflow of Post-counter register at Spresense SDK?
- I dont know my assumption right or wrong ? Below is my assumption.
Will Spesense generate an interrupt when Post-counter register is overflow every 36.4 hours ? So Spresense will use this IRQ to correct the rtc saving time at ISR of this IRQ ?